In recent years, a technique to form a thin film transistor (hereinafter referred to as a TFT in this specification) over a substrate has been drastically advanced and developed for an application to an active matrix display device. In particular, a TFT using a polycrystalline semiconductor film such as polysilicon is higher than a conventional TFT using an amorphous semiconductor film such as amorphous silicon in field effect mobility (also referred to as mobility), which enables a fast operation. Accordingly, pixels which are conventionally controlled by a driver circuit outside a substrate can now be controlled by a driver circuit formed over the same substrate as the pixels.
In an active matrix display device using such a polycrystalline semiconductor film, various circuits and elements can be formed over the same substrate. Therefore, there are various advantages such as reduction in manufacturing cost, downsizing of a display device, improvement of yield, and reduction of throughput.
Further, a research on an active matrix EL display device using an EL element as a self-luminous element has been activated. An EL display device is also referred to as an organic EL display (OLED) or an organic light emitting diode (OLED).
An EL element has a structure in which a pair of electrodes (anode and cathode) sandwich an EL layer which normally has a stacked-layer structure. Typically, there is a stacked layer structure of “a hole transporting layer, a light emitting layer, and an electron transporting layer” suggested by Tang et al. at Eastman Kodak Company. This structure has quite high light emitting efficiency and is employed for most EL display devices now being researched and developed.
Besides, a stacked-layer structure of a hole injecting layer, a hole transporting layer, a light emitting layer, and an electron transporting layer or a stacked-layer structure of a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer over an anode may be employed as well. The light emitting layer may be doped with a phosphorescence pigment and the like.
In this specification, all layers provided between a cathode and an anode are collectively referred to as an EL layer. Therefore, the hole injecting layer, the hole transporting layer, the light emitting layer, the electron transporting layer, the electron injecting layer and the like are all included in the EL layer.
When a predetermined voltage is applied to an EL layer with the aforementioned structure from the pair of electrodes, carriers are recombined in the light emitting layer and light is emitted. In this specification, when an EL element emits light, it is referred that EL element is driven. Further in this specification, a light emitting element formed of an anode, an EL layer, and a cathode is referred to as an EL element.
It is to be noted in this specification that an EL element may utilize both light emission (phosphorescence) which occurs from a singlet excitation state and light emission (fluorescence) which occurs from a triplet excitation state.
An EL display device may be driven by an analog driving method (analog drive) and a digital driving method (digital drive). First, description is made with reference to FIGS. 1 and 2 on the analog drive of an EL display device.
FIG. 1 shows a structure of a pixel portion 100 of an analog drive EL display device. Gate signal lines (G1 to Gy) each of which is inputted with a selection signal from a gate signal line driver circuit is connected to a gate electrode of a switching TFT 101 of each pixel. One of a source region and a drain region of the switching TFT 101 of each pixel is connected to each of source signal lines (also referred to as a data signal line) (S1 to Sx) which is inputted with an analog video signal and the other is connected to a gate electrode of a driving TFT 104 and a capacitor 108 of each pixel.
One of a source region and a drain region of the driving TFT 104 of each pixel is connected to each of power supply lines (V1 to Vx) and the other is connected to an EL element 106. A potential of each of the power supply lines (V1 to Vx) is referred to as a power source potential. Each of the power supply lines (V1 to Vx) is connected to the capacitor 108 of each pixel.
The EL element 106 has an anode, a cathode, and an EL layer provided between the anode and the cathode. In the case where the anode of the EL element 106 is connected to the source region or the drain region of the driving TFT 104, the anode of the EL element 106 is a pixel electrode while the cathode thereof is a counter electrode. In the case where the cathode of the EL element 106 is connected to the source region or the drain region of the driving TFT 104, the anode of the EL element 106 is a counter electrode while the cathode thereof is a pixel electrode.
In this specification, a potential of a counter electrode is referred to as a counter potential. A power source which applies a counter potential to a counter electrode is referred to as a counter power source. A potential difference between a potential of a pixel electrode and a potential of a counter electrode is an EL driving voltage which is applied to an EL layer.
FIG. 2 shows a timing chart of the EL display device shown in FIG. 1 driven by an analog method. A period from selection of one gate signal line until the selection of a different gate signal line is referred to as one line period (L). A period from a display of one image until a display of a next image corresponds to one frame period (F). In the case of the EL display device of FIG. 1, there are y gate signal lines, therefore, y line periods (L1 to Ly) are provided in one frame period.
The power supply lines V1 to Vx are held at a certain power source potential. The counter potential which is a potential of the counter electrode is also held at a certain potential. The counter potential and the power source potential have a potential difference such that an EL element emits light.
In a first line period (L1), the gate signal line G1 is inputted with a selection signal from a gate signal line driver circuit. Then, analog video signals are sequentially inputted to the source signal lines S1 to Sx. Since all switching TFTs connected to the gate signal line G1 are turned on, the analog video signals inputted to the source signal lines S1 to Sx are inputted through the switching TFTs to the gate electrodes of the driving TFTs.
The amount of current flowing through a channel forming region of a driving TFT is controlled by a gate voltage thereof.
Here, description is made on an example where a source region of a driving TFT is connected to a power supply line and a drain region thereof is connected to an EL element.
As the source region of the driving TFT is connected to the power supply line, each pixel in a pixel portion is inputted with the same potential. At this time, when an analog signal is inputted to a source signal line, a potential difference between a potential of the signal voltage and a potential of the source region of the driving TFT becomes a gate voltage. A current flowing to an EL element depends on a gate voltage of the driving TFT. Here, luminance of the EL element is in proportion with a current flowing between opposite electrodes of the EL element. In this manner, an EL element emits light depending on a voltage of an analog video signal.
The aforementioned operation is repeated, and when analog video signals are inputted to all the source signal lines (S1 to Sx), the first line period (L1) ends. It is to be noted that the period until the analog video signals are all inputted and a horizontal retrace line period together may be one line period. Then, in a second line period (L2), the gate signal line G2 is inputted with a selection signal. Similarly to the case of the first line period (L1), analog video signals are sequentially inputted to the source signal lines (S1 to Sx).
When the selection signals are inputted to all the gate signal lines (G1 to Gy), all the line periods (L1 to Ly) end. When all the line periods (L1 to Ly) end, one frame period ends. In one frame period, all the pixels perform display to form one image. It is to be noted that all the line periods (L1 to Ly) and a vertical retrace line period together may be one frame period.
As described above, the amount of light emitted by an EL element is controlled by an analog video signal. By controlling the amount of light emission, a gray scale display is performed. This method is a so-called analog driving method, where a gray scale display is performed by changing a voltage of an analog video signal inputted to the source signal line.
Next, description is made on a digital drive of an EL display device. In a digital gray scale method, a gate-source voltage Vg of the driving TFT 104 operates in two stages: either in a region (equal to a light emission start voltage or lower) that no current flows to the EL element 106 or a region (equal to a luminance saturation voltage or higher) that the largest current flows thereto. That is, an EL element either emits light or emits no light.
An EL display mainly employs the digital gray scale method in which variations in characteristics such as a threshold value of a TFT do not easily affect a display. In the case of the digital gray scale method, however, only two gray scale levels can be displayed by itself. Therefore, a plurality of techniques to employ the digital gray scale method in combination with another method are suggested to perform a multi gray scale display.
One of these techniques is a method of using an area gray scale method and the digital gray scale method in combination. The area gray scale method is a method for displaying gray scales by controlling the area of portions which emit light. That is, one pixel is divided into a plurality of subpixels, and the number and the area of subpixels which emit light are controlled to display a gray scale. This method is disadvantageous in that high resolution and multi gray scales display cannot be easily achieved as the number of subpixels cannot be increased. Non-patent Documents 1, 2, and the like disclose the area gray scale method.
Another method to achieve a multi gray scale display is a method for using a time gray scale method and the digital gray scale method in combination. The time gray scale method is a method for displaying gray scales by utilizing a difference in light emission time. That is, one frame period is divided into a plurality of subframe periods, and gray scales are displayed by controlling the number and length of the subframe periods in which light is emitted (see Patent Document 1).
Non-patent Document 3 discloses the case of using the digital gray scale method, the area gray scale method, and the time gray scale method in combination.
Next, description is made on a constant current drive and a constant voltage drive in the case of displaying gray scales by the digital gray scale method.
The constant current drive is a driving method to operate the driving TFT 104 in a saturation region when the EL element 106 emits light and supply a constant current to all pixels. This driving method is advantageous in that a constant current can be supplied to the EL element 106 even when the EL element 106 deteriorates and V-I characteristics change, which leads to prolong life of an EL display device.
On the other hand, the constant voltage drive is a driving method to operate the driving TFT 104 in a linear region when the EL element 106 emits light and supply a constant voltage to all pixels. This driving method is advantageous in that a constant voltage can be applied to the EL element 106 even when characteristics of the driving TFT 104 vary, which leads to no variations in luminance of pixels and high display quality.    [Non-patent Document 1]    Euro Display 99 Late News: P71: “TFT-LEPD with Image Uniformity by Area Ratio Gray Scale”    [Non-patent Document 2]    IEDM 99: P107: “Technology for Active Matrix Light Emitting Polymer Displays”    [Non-patent Document 3]    IDW'99: P171: “Low-Temperature Poly-Si TFT Driven Light-Emitting-Polymer Displays and Digital Gray Scale for Uniformity”    [Patent Document 1]    Japanese Patent Laid-open No. 2001-324958